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3.3V CMOS Static RAM 4 Meg (512K x 8-Bit)
Features
512K x 8 advanced high-speed CMOS Static RAM JEDEC Center Power / GND pinout for reduced noise Equal access and cycle times -- Commercial and Industrial: 10/12/15ns Single 3.3V power supply One Chip Select plus one Output Enable pin Bidirectional data inputs and outputs directly TTL-compatible Low power consumption via chip deselect Available in 36-pin, 400 mil plastic SOJ package and 44-pin, 400 mil TSOP.
IDT71V424S IDT71V424L
x x x
Description
The IDT71V424 is a 4,194,304-bit high-speed Static RAM organized as 512K x 8. It is fabricated using IDT's high-perfomance, high-reliability CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for highspeed memory needs. The IDT71V424 has an output enable pin which operates as fast as 5ns, with address access times as fast as 10ns. All bidirectional inputs and outputs of the IDT71V424 are TTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. The IDT71V424 is packaged in a 36-pin, 400 mil Plastic SOJ and 44pin, 400 mil TSOP.
x x x
x x
Functional Block Diagram
A0
A18
* * *
ADDRESS DECODER
* * *
4,194,304-BIT MEMORY ARRAY
I/O0 - I/O7
8
8
I/O CONTROL
8
WE OE CS
CONTROL LOGIC
3622 drw 01
JULY 2003
1
(c)2003 Integrated Device Technology, Inc. DSC-3622/05
IDT71V424S, IDT71V424L, 3.3V CMOS Static RAM 4 Meg (512K x 8-bit)
Commercial and Industrial Temperature Ranges
Pin Configuration
A0 A1 A2 A3 A4 CS I/O 0 I/O 1 VDD VSS I/O 2 I/O 3 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 NC A18 A17 A16 A15 OE I/O 7 I/O 6 VSS VDD I/O 5 I/O 4 A14 A13 A12 A11 A10 NC
3622 drw 02
Pin Configuration
NC NC A0 A1 A2 A3 A4 CS I/00 I/01 V DD V SS I/02 I/03 WE A5 A6 A7 A8 A9 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 SO44-2 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 NC NC NC A18 A17 A16 A15 OE I/07 I/06 V SS V DD I/05 I/04 A14 A13 A12 A11 A10 NC NC NC
SO36-1
SOJ Top View
TSOP Top View Pin Description
A0 - A18 CS WE OE I/O0 - I/O7 VDD VSS Address Inputs Chip Select Write Enable Output Enable Data Input/Output 3.3V Power Ground Input Input Input Input I/O Power Gnd
3622 tbl 02
3622 drw 11
Capacitance
(TA = +25C, f = 1.0MHz, SOJ package)
Symbol CIN CI/O Parameter(1) Input Capacitance I/O Capacitance Conditions VIN = 3dV VOUT = 3dV Max. 7 8 Unit pF pF
3622 tbl 03
NOTE: 1. This parameter is guaranteed by device characterization, but not production tested.
Truth Table(1,2)
CS L L L H VHC
(3)
OE L X H X X
WE H L H X X
I/O
Function
DATAOUT Read Data DATAIN High-Z High-Z High-Z Write Data Output Disabled Deselected - Standby (ISB) Deselected - Standby (ISB1)
3622 tbl 01
NOTES: 1. H = VIH, L = VIL, x = Don't care. 2. VLC = 0.2V, VHC = VDD -0.2V. 3. Other inputs VHC or VLC.
6.42 2
IDT71V424S, IDT71V424L, 3.3V CMOS Static RAM 4 Meg (512K x 8-bit)
Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings(1)
Symbol VDD VIN, VOUT TBIAS TSTG PT IOUT Rating Supply Voltage Relative to VSS Terminal Voltage Relative to VSS Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Value -0.5 to +4.6 -0.5 to VDD+0.5 -55 to +125 -55 to +125 1 50 Unit V V
o o
Recommended Operating Temperature and Supply Voltage
Grade C om m ercial Indu stria l Temperature 0 C to + 70 C -40 C to + 8 5 C VS S 0V 0V VDD S ee B elow S ee B elow
3 622 tbl 0 5
C C
W mA
3622 tbl 04
Recommended DC Operating Conditions
Symbol VDD VSS VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 3.0 0 2.0 -0.3
(2)
Typ. 3.3 0
____ ____
Max. 3.6 0 VDD+0.3 0.8
(1)
Unit V V V V
3622 tbl 06
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
NOTES: 1. VIH (max.) = VDD+2V for pulse width less than 5ns, once per cycle. 2. VIL (min.) = -2V for pulse width less than 5ns, once per cycle.
DC Electrical Characteristics
(VDD = Min. to Max., Commercial and Industrial Temperature Ranges)
IDT71V424 Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Test Condition VDD = Max., VIN = VSS to VDD VDD = Max., CS = VIH, VOUT = VSS to VDD IOL = 8mA, VDD = Min. IOH = -4mA, VDD = Min. Min.
___ ___ ___
Max. Unit 5 5 0.4
___
A A V V
3622 tbl 07
2.4
DC Electrical Characteristics(1, 2, 3)
(VDD = Min. to Max., VLC = 0.2V, VHC = VDD - 0.2V)
71V424S/L10 Symbol ICC Parameter D y nam ic O perating C urrent CS V LC, O utpu ts O pen, V DD = M a x., f = fM A X(4 ) D y nam ic S tand by P ow er S up ply C u rrent CS V HC, O utpu ts O pen, V DD = M a x., f = fM A X (4 ) Full Stan dby P ow er Su pply C urrent (static) CS V HC, O utpu ts O pen, V DD = M a x., f = 0 (4 ) S L S L S L Com'l. 180 165 60 45 20 10 Ind.
(5 )
71V424S/L12 Com'l. 170 155 50 40 20 10 Ind. 170 155 50 40 20 10
71V424S/L15 Com'l. 160 145 40 35 20 10 Ind. 160 145 40 35 20 10 U nit mA mA mA mA mA mA
362 2 tbl 0 8
180 -- 60 -- 20 --
IS B
ISB1
NOTES: 1. All values are maximum guaranteed values. 2. All inputs switch between 0.2V (Low) and VDD - 0.2V (High). 3. Power specifications are preliminary. 4. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing. 5. Standard power 10ns (S10) speed grade only.
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IDT71V424S, IDT71V424L, 3.3V CMOS Static RAM 4 Meg (512K x 8-bit)
Commercial and Industrial Temperature Ranges
AC Test Conditions
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load GND to 3.0V 1.5ns 1.5V 1.5V See Figure 1, 2 and 3
3622 tbl 09
AC Test Loads
+1.5V 50 I/O Z0 = 50 30pF
3622 drw 03
3.3V 320 DATAOUT 5pF* 350
3622 drw 04
*Including jig and scope capacitance.
Figure 1. AC Test Load Figure 2. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
7
*
6 tAA, tACS (Typical, ns) 5 4 3
* *
2 1
* * *
*
8 20
40
60 80 100 120 140 160 180 200 CAPACITANCE (pF)
Figure 3. Output Capacitive Derating
3622 drw 05
6.42 4
IDT71V424S, IDT71V424L, 3.3V CMOS Static RAM 4 Meg (512K x 8-bit)
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VCC = 3.3V 10%, Commercial and Industrial Temperature Ranges)
71V424S/L10(2) Symbol READ CYCLE tRC tAA tACS tCLZ (1) tCHZ(1) tOE tOLZ(1) tOHZ(1) tOH tPU(1) tPD(1) WRITE CYCLE tWC tAW tCW tAS tWP tWR tDW tDH tOW
(1)
71V424S/L12 Min. Max.
71V424S/L15 Min. Max. Unit
Parameter
Min.
Max.
Read Cycle Time Address Access Time Chip Select Access Time Chip Select to Output in Low-Z Chip Deselect to Output in High-Z Output Enable to Output Valid Output Enable to Output in Low-Z Output Disable to Output in High-Z Output Hold from Address Change Chip Select to Power Up Time Chip Deselect to Power Down Time
10
____ ____
____
12
____ ____
____
15
____ ____
____
ns ns ns ns ns ns ns ns ns ns ns
10 10
____
12 12
____
15 15
____
4
____
4
____
4
____
5 5
____
6 6
____
7 7
____
____
____
____
0
____
0
____
0
____
5
____
6
____
7
____
4 0
____
4 0
____
4 0
____
____
____
____
10
12
15
Write Cycle Time Address Valid to End of Write Chip Select to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid to End of Write Data Hold Time Output Active from End of Write Write Enable to Output in High-Z
10 8 8 0 8 0 6 0 3
____
____ ____ ____ ____ ____ ____ ____ ____
12 8 8 0 8 0 6 0 3
____
____ ____ ____ ____ ____ ____ ____ ____
15 10 10 0 10 0 7 0 3
____
____ ____ ____ ____ ____ ____ ____ ____
ns ns ns ns ns ns ns ns ns ns
3622 tbl 10
____
____
____
tWHZ(1)
6
7
7
NOTES: 1. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested. 2. 0C to +70C temperature range only for low power 10ns (L10) speed grade.
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IDT71V424S, IDT71V424L, 3.3V CMOS Static RAM 4 Meg (512K x 8-bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 1(1)
tRC ADDRESS tAA OE tOE CS tOLZ
(5) (5) (3)
tACS
tCLZ DATAOUT
tCHZ
(5)
tOHZ (5)
HIGH IMPEDANCE
DATAOUT VALID tPD
VCC SUPPLY ICC CURRENT ISB
tPU
3622 drw 06
Timing Waveform of Read Cycle No. 2(1, 2, 4)
tRC ADDRESS tAA tOH DATAOUT PREVIOUS DATAOUT VALID tOH DATAOUT VALID
3622 drw 07
NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected, CS is LOW. 3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter. 4. OE is LOW. 5. Transition is measured 200mV from steady state.
6.42 6
IDT71V424S, IDT71V424L, 3.3V CMOS Static RAM 4 Meg (512K x 8-bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1, 2, 4)
tWC ADDRESS tAW CS tWR tAS WE tWHZ DATAOUT
(3) (5)
tWP (2) tCHZ (5)
(3)
tOW HIGH IMPEDANCE tDW tDH
(5)
DATAIN
DATAIN VALID
3622 drw 08
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1, 4)
tWC ADDRESS tAW CS
tAS WE
tCW
tWR
tDW DATAIN DATAIN VALID
tDH
3622 drw 09
NOTES: 1. A write occurs during the overlap of a LOW CS and a LOW WE. 2. OE is continuously HIGH. During a WE controlled write cycle with OE LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is the specified tWP. 3. During this period, I/O pins are in the output state, and input signals must not be applied. 4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high impedance state. CS must be active during the tCW write period. 5. Transition is measured 200mV from steady state.
6.42 7
IDT71V424S, IDT71V424L, 3.3V CMOS Static RAM 4 Meg (512K x 8-bit)
Commercial and Industrial Temperature Ranges
Ordering Information
IDT 71V424 Device Type X Die Revision X Power XX Speed XXX Package X Process/ Temperature Range Blank I Commercial (0C to +70C) Industrial (-40C to +85C)
Y PH
36-pin 400 mil SOJ (SO36-1) 44-pin TSOP Type II (SO44-2)
10* 12 15
Speed in nanoseconds
S L Blank Y
Standard Power Low Power First Generation or current stepping being shipped Second Generation die step
* Commercial only for low power 10ns (L10) speed grade.
3622 drw 10
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IDT71V424S, IDT71V424L, 3.3V CMOS Static RAM 4 Meg (512K x 8-bit)
Commercial and Industrial Temperature Ranges
Datasheet Document History
8/13/99 Pg. 2 Pg. 7 Pg. 9 Pg. 1-9 Pg. 8 Pg. 8 Updated to new format Removed SO44-1 from TSOP pinout Revised footnotes on Write Cycle No. 1 diagram Removed footnote for tWR on Write Cycle No. 2 diagram Added Datasheet Document History Added Industrial temperature range offerings Added die revision option to ordering information Updated note, L10 speed grade commercial temperature only and updated die stepping from YF to Y.
8/31/99 11/22/02 07/31/03
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for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: sramhelp@idt.com 800-544-7726, x4033
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
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